As the semiconductor industry continues to grow, the need to develop increasingly complex integrated circuits with smaller feature sizes and dimensions has been highly sought after. Driven by the demand for high performance, chip scale packaging technologies have been applied to the packaging of individual integrated circuit dies at wafer-level in order to meet requirements for high integration, weight lightening, thickness reduction, shortening the length and miniaturization of the integrated circuit package.
As one example of the chip scale packaging technologies, there is a wafer level fan-out package (WLFOP) in which an individual integrated circuit die is embedded in a molding compound with space allocated between each integrated circuit die for additional input/output (I/O) connection points. The integrated circuit dies and the molding compound are then mounted on a wafer substrate containing conductive lines (also referred to herein as a “redistribution wafer”). In the WLFOP technology, passive components such as inductors are typically formed on, embedded, or otherwise integrated into the wafer substrate.
However, a reduction of the overall package size (e.g., form factor) of a WLFOP becomes difficult due to the arrangements of the passive components in the proximity of the conductive lines in the wafer area. Such a configuration may result in an increased likelihood of cross-talk and signal interference, which may degrade package reliability and performance, as well as making such packages more difficult to assemble in a high volume product.